Monday (July 10, 2000)
8:00 Registeration
8:45 Introduction to the Conference - Earl Swartzlander, the University of Texas at Austin
9:00 Keynote Talk

• "High-Performance Front-End Embedded Signal Processors for Adaptive Sensor Arrays", Bill Song, MIT Lincoln Laboratory

• "Subword Permutation Instructions for Two-Dimensional Multimedia Processing in MicroSIMD Architectures", Ruby Lee, Princeton University.

• "Architecture of an Image Rendering Co-processor for MPEG-4 Systems, M. Berekovic, P.Pirsch, T. Selinger, K.-I- Wels, C. Miro, A. Lafage, C. Heer, and G. Ghigo, Universitaet Hannover, Heinrich-Hertz-Institut,ENST, Siemens AG, and CSELT.

• "A Multiplication-Free Parallel Architecture for Affine Transformation", Wael Badawy and Magdy Bayoumi, University of Louisiana.

• "A Simple RISC Microprocessor Core Design for Digital Set-Top-BoxApplications", Marco Antonio Simon Dal Poz, Jose Edinson Aedo Cobo, Marcelo Knorich Zuffo, and Wilhelmus Adrianus Maria Van Noije, Cidade Universitaria.

• "Formal Verification for Microprocessors with Extendable Instruction Set", Sergej Sawitzki, Rainer G. Spallek, Jens Schoenherr, and Bernd Straube, Dresden University of Technology and Fraunhofer Institut Integrierte Schaltungen Erlangen.

• "Compiling Image Processing Applications to Reconfigurable Hardware", Robert Rinker, Jeff Hammes, Walid A. Najjar, Wim Bohm, and Bruce Draper, Colorado State University.

• "Integration of High-Performance ASICs into Reconfigurable Systems Providing Additional Multimedia Functionality", Holger Blume, Hans-Martin Bluethgen, Christiane Henning, and Patrick Osterloh, University of Technology RWTH Aachen.

• "High Level Modeling for Parallel Executions of Nested Loop Algorithms", Ed F. Deprettere, Edwin Rijpkema, Paul Lieverse, and Bart Kienhuis, Leiden University, Delft University of Technology, and the University of California, Berkeley.

• "Minimal Design Complexity Loop Representations of SFG Processors for Optimal Synthesis", Andrew Stone and Elias S. Manolakos, Northeastern University.

• "High Level Synthesis for Peak Power Minimization using ILP", Wen-Tsong Shiue, Arizona State University.

• "High-Level Synthesis of Nonprogrammable Hardware Accelerators", Robert Schreiber, Shail Aditya, B. Ramakrishna Rau, Vinod Kathail, Scott Mahlke, Santosh Abraham, and Greg Snider, Hewlett-Packard Labs.

Tuesday (July 11, 2000)
8:30 Session 4 - Cryptography (Chair: Ruby Lee, Prineton University)

• "Implementing 1,024-bit RSA Exponentiation on a 32-bit Processor Core", Braden J. Phillips and Neil Burgess", University of Adelaide and Cardiff University.

• "Bit Permutation Instructions for Accelerating Software Cryptography", Zhijie Shi and Ruby B. Lee, Princeton University.

• "Performance-Scalable Array Architectures for Modular Multiplication", William L. Freking and Keshab K. Parhi, University of Minnesota.

• "A High-Throughput 1D-DCT Architecture", Ahmed Shams and Magdy Bayoumi, The University of Louisiana at Lafayette.

• "Efficient VLSI Architectures for Baseband Signal Processing in Wireless Base-Station Receivers", Sridhar Rajagopal, Srikrishna Bhashyam, Joseph R. Cavallaro, and Behnaam Aazhang, Rice University.

• "A Vector Multiprocessor for Real-Time Multi-User Detection in Spread-Spectrum Communication", Naraig Manjikian, Queen's University.

• "A 550 Mb/s Radix-4 Bit-level Pipelined 16-State 0.25-um CMOS Viterbi Decoder", V.S. Gierenz, O. Weiss, T.G. Noll, I. Carew, J. Ashley, R. Karabed, and J. Rae, Aachen Institute of Technology and Infineon Technologies

• "A Booth Multiplier Accepting Both a Redundant or a Non-Redundant Input with no Additional Delay", Marc Daumas and David W. Matula, ENS de Lyon - INRIA, and Southern Methodist University.

• "A Hardware Algorithm for Variable-Precision Logarithm", Javier Hormigo, Julio Villalba, and Michael Schulte, University of Malaga and Lehigh University.

• "Block-Update Parallel Processing QRD-RLS Algorithm for Throughput Improvement with Low Power Consumption, Lijun Gao and Keshab K. Parhi, University of Minnesota.

• "A 16-bit x 16-bit MAC Design Using Fast 5:2 Compressors", Ohsang Kwon, Kevin Nowka, and Earl E. Swartzlander, Jr., IBM Austin Research Lab and the University of Texas at Austin.

15:45 Cofee Break
16:00 Session 7 - Multiprocessor Systems (Chair: Ed Deprettere, Leiden University)
 

• "Control for High-Speed PE Arrays", Martin C. Herbordt, Jade Cravy, Honghai Zhang, Calvin Lin, and Hong Rao, University of Houston and GDA Technologies.

• "Explicit SIMD Programming for Asynchronous Applications", Andrea Di Blas and Richard Hughey, University of California, Santa Cruz.

• "Quadratic Control in Linear Systolic Arrays", Scott Bowden, Doran Wilde, and Sanjay Rajopadhye, Brigham Young University.

• "Contention-conscious Transaction Ordering in Embedded Multiprocessors", Mukul Khandelia and Shuvra S. Bhattacharyya, University of Maryland at College Park.

Wednesday (July 12, 2000)
8:00 Session 8 - Application-specific Architectures (Chair: Neil Burgess, Cardiff University)
 

• "Architecture for Wavelet Packet Transform with Best Tree Searching" Maria A. Trenas, Juan Lopez, Manuel Sanchez, and Emilio L. Zapata, Francisco Arguello, Universidad de Malaga.

• "Tradeoff Analysis and Architecture Design of a Hybrid Hardware/Software Sorter", Marcus Bednara, Oliver Beyer, Juergen Teich, and Rolf Wanka, Paderborn University.

• "A Programmable Processor for Approximate String Matching With High Throughput Rate", Hans-Martin Bluethgen and Tobias Noll, University of Technology RWTH Aachen.

• "A New Algorithm for the Elimination of Common Subexpressions in Hardware Implementation of Digital Filters by Using Genetic Programming", H. Safiri, M. Ahmadi, G. A. Jullien, and W. C. Miller, The University of Windsor.

• "A Theory for Software-Hardware Co-Scheduling for ASIPs and Embedded Processors" R. Govindarajan, Erik R. Altman, and Guang R. Gao, Indian Institute of Science, IBM T.J. Watson Research Center, and the University of Delaware.

• "Partitioning Conditional Data Flow Graphs for Embedded System Design" Michel Auguin, Luc Bianco, Laurent Capella, and Emmanuel Gresset, Les Algorithmes and Philips.

• "Generation of Scheduling Functions Supporting LSGP-Partitioning" Dirk Fimmel, Dresden University of Technology.

11:00 Close of Conference