Steven Fortune, Technical Manager of the Algorithms Research Group

Bell Labs, Alcatel-Lucent

Towards Massively Scalable IP Routers

Tuesday, November 27, 4:00 PM

Packard Lab, Room 466

Reception prior to talk at 3:30 in Packard Lobby

Abstract: Internet traffic is increasing at an exponential rate, variously estimated at 30% or more per year, with no end of growth in sight.  But underlying communication technologies may not be able to keep up: we are approaching the per-channel spectral capacity limits of dense wave-division multiplexing (perhaps peaking around a terabit/second per channel), and while VLSI feature size continues to decrease and transistor count increase, VLSI clock rate will decrease only slightly. These trends argue that future core IP routers will require both significantly increased switching capacity and increased port count. Parallelism, at all levels from VLSI pipeling to router architecture, will be required. Load-balancing, proposed slightly more than a decade ago in the context of switch fabrics, provides architectural parallelism. I will discuss some practical contributions to the design of load-balanced switch fabrics, addressing the well-known problem of cell reordering as well as mid-stage congestion control and buffer sizing.

Bio: Dr. Fortune received his Ph.D from Cornell University in 1979 in Computer Science and has been at Bell Laboratories in Murray Hill since 1983.  He is currently Technical Manager of the Algorithms Research group, overseeing a variety of applied and theoretical research projects in algorithms, networking, and theoretical computer science.

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