Graduate Student Posters 2007

Authors: Ryan Templin, Jeremy Tallman

Verilog implements fork() and join() operators, which allow code to be executed in parallel thus accurately modeling hardware. While in some cases this can be done by using many separate always blocks it is more convenient and logical to use the fork()/join() operators available in Verilog. VITO, a synthesis preprocessor takes the code between fork() and join() and creates separate while loops using a one-hot design method. Special join registers are created which allow for control between the parallel executing blocks within the fork() and join() operators, thus creating a synthesizable machine.