The content on this page is the work of Professor Mark Arnold. Although these pages remain active as a courtesy, Professor Arnold is no longer on the Lehigh faculty and the content may be no longer current or accurate
DLX in VHDL
The DLX processor is a theoretical microprocessor. To my knowledge
it has never been fabricated in silicon for comercial sale. Its main
purpose is to allow people to study, teach, and practice with microprocessor
design. The DLX instruction set architecture is very similar to MIPS,
although they have some differences. DLX is a load/store, RISC architecture.
The goal of my project was to design a VHDL model of the DLX
processor. In my VHDL implementation of DLX, most instructions require
5 clock cycles to complete, however, jumps need only 3. Floating point
timing is not completely accurate because floating point instructions
also take only 5 cycles to complete.
Some of the more formidable accomplisments in this design were:
Download the VHDL source code
Giving the processor the ability to use a file on the hard drive
as a program ROM. This allowed for easy program modifications
Designing the processor to be multi-cycle. This made going back and using
microcode control easy.
Converting the processor to let it use microcode that loads from
a data file. This will hopefully make it easier to pipline the processor.
Although I used a public domain floating point adder and multiplier,
the concepts of floating point addition and multiplication needed to be
understood to make the necessary changes so that these units could handle
double precision numbers and all four IEEE rounding modes.
The floating point divider was a project in itself because of the
fact that I built it from scratch. Unlike the floating point adder and
multiplier, which are procedurally designed, I created the divider as a
structural entity. It, like the other floating point units, is capable
of both single and double precision as well as using the four rounding
Acknowledgement: This project was supported by a National Science
Foundation Research Experience for Undergraduates Award.
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