The goal of my project was to design a VHDL model of the DLX processor. In my VHDL implementation of DLX, most instructions require 5 clock cycles to complete, however, jumps need only 3. Floating point timing is not completely accurate because floating point instructions also take only 5 cycles to complete. Some of the more formidable accomplisments in this design were:

• Giving the processor the ability to use a file on the hard drive as a program ROM. This allowed for easy program modifications
• Designing the processor to be multi-cycle. This made going back and using microcode control easy.
• Converting the processor to let it use microcode that loads from a data file. This will hopefully make it easier to pipline the processor.
• Although I used a public domain floating point adder and multiplier, the concepts of floating point addition and multiplication needed to be understood to make the necessary changes so that these units could handle double precision numbers and all four IEEE rounding modes.
• The floating point divider was a project in itself because of the fact that I built it from scratch. Unlike the floating point adder and multiplier, which are procedurally designed, I created the divider as a structural entity. It, like the other floating point units, is capable of both single and double precision as well as using the four rounding modes.