Research and Education Publications

Section 1: Prof. Mark Arnold

• P. D. Vouzis, S. Collange, M. G. Arnold, “A Novel Cotransformation for LNS Subtraction,” Submitted to the Journal of VLSI Signal Processing Systems, November 2007.

• P. Vouzis, L. Bleris, M. Arnold, M. Kothare,  "A System-on-a-Chip Implementation for Embedded Real-Time Model Predictive Control," Accepted by the IEEE Transactions on Control Systems Technology, March 2007.

• L. G. Bleris, P. D. Vouzis, J. G. Garcia, M. G. Arnold and M. V. Kothare, "Pathways for Optimization-based Drug Delivery,"  in Special Issue of Control Engineering Practice Journal for the 2006 ADCHEM Symposium, vol. 15, issue 10, pp. 1280–1291, October 2007 (Invited paper). (CEP Link)

• L. G. Bleris, J. G. Garcia, Mark G. Arnold, Mayuresh V. Kothare, "Model Predictive Hydrodynamic Regulation of Microflows," Journal of Micromechanics & Microengineering, vol. 16, pp. 1792-1799, July 2006. (JMM Link)

• L. G. Bleris, J. Garcia, M. V. Kothare and M. G. Arnold, " Towards embedded model predictive control for System-on-a-Chip applications," Journal of Process Control, Vol. 16, No. 3, pp. 255-264, March 2006. (JPC Link)
  

• M. Arnold, T. Bailey, J. Cowles and C. Walter, ''Fast Fourier Transforms using the Complex Logarithm Number System,'' J. VLSI Signal Proc., vol 33, pp. 325-335, 2003. (JVLSI Link)

• M. Arnold, T. Bailey, and J. Cowles, "Error Analysis of the Kmetz/Maenner Algorithm," J. VLSI Signal Proc., vol 33, pp. 37-53, 2002. (JVLSI Link)

• M. G. Arnold, T. A. Bailey, J. R. Cowles and M. D. Winkel, "Arithmetic Co-transformations in the Real and Complex Logarithmic Number Systems," IEEE Trans. On Computers, vol. 7, pp. 777-786, 1998. (IEEE ToC Link)

• M. Arnold, T. Bailey, J. Cowles and M. Winkel, "Applying Features of IEEE 754 to Sign/logarithm Arithmetic," IEEE Trans. On Computers, vol. 8, Special Issue on Computer Arithmetic, pp. 1040-1050, 1992. (IEEE ToC Link)

• M. Arnold, T. Bailey and J. Cowles, "Comments on 'An Architecture for Addition and Subtraction of Long Word Length Numbers in the Logarithmic Number System' by D.M. Lewis," IEEE Trans. On Computers vol. 6, pp. 786-788, 1992. (IEEE ToC Link)

• M. Arnold, T. Bailey, J. Cowles and J. Cupal, "Initializing RAM-based Logarithmic Processors," J. VLSI Sig. Proc. vol. 4, pp. 243-252, 1992. (JVLSI Link)

• M. Arnold, T. Bailey, J. Cowles and J. Cupal, "Redundant Logarithmic Arithmetic," IEEE Transactions on Computers vol. 39, Special Issue on Computer Arithmetic, pp. 1077-1086, 1990. (12/68) (IEEE ToC Link)

• M. G. Arnold, Verilog Digital Computer Design: Algorithms into Hardware, PTR Prentice Hall: Upper Saddle River, New Jersey, 602 pp., 1999.

• P. Vouzis, S. Collange, M. Arnold, "Cotransformation Provides Area and Accuracy Improvement in an HDL Library for LNS Subtraction," in Proceedings of the 10^th EuroMicro Conference on Digital System Design, pp. 85-93, Lübeck, Germany, 27-31 August, 2007. (PDF File)

• M. Arnold, P. Vouzis, "A Serial Logarithmic Number System ALU," in Proceedings of the 10^th EuroMicro Conference on Digital System Design, pp. 151-154, Lübeck, Germany, 27-31 August, 2007. (PDF File)

• P. Vouzis, S. Collange, M. Arnold, M. Kothare, "Monte Carlo Logarithmic Number System for Model Predictive Control," in Proceedings of the 17^th International Conference on Field Programmable Logic and Applications, pp. 453-458, Amsterdam, Netherlands, 27-29 August, 2007. (PDF File)

• P. Vouzis, S. Collange, M. Arnold, "LNS Subtraction Using Novel Cotransformation and/or Interpolation,"  In Proceedings of the  IEEE 18^th International Conference on Application-specific Systems, Architectures and Processors , pp. 107-114, Montréal, Québec, Canada, 9-11 July, 2007 (Best Paper Award). (PDF File)(PowerPoint Presentation)

• P. Vouzis, M. Arnold, L. Bleris, M. Arnold, M. Kothare, Yongho Cha, "A Coprocessor Accelerator for Model Predictive Control," in Proceedings of the 5^th Workshop on Optimization for DSP and Embedded Systems, pp. 76-77, San Jose, CA, March 11, 2007. (PDF File)

• P. Vouzis, L. Bleris, M. Arnold, M. Kothare, "Model Predictive Control for Embedded Applications," in AIChE annual meeting, November 2006. (AIChE Link) (PowerPoint Presentation)

• P. Vouzis, M. Kothare, M. Arnold, "Evaluating Robustness of Model Predictive Control Using Monte Carlo Simulations," in AIChE annual meeting, November 2006. (AIChE Link) (PowerPoint Presentation)

• Mark G. Arnold, "A RISC Processor with Redundant LNS Instructions," In EuroMicro Digital System Design DSD, pp. 475-482, Dubrovnik, Croatia, Aug.-1 Sept. 2006.

• D. Coleman, J. Spletzer and M. G. Arnold, "Target-Logic Circuits Built with Holonomic Field Programmable Robot Arrays," Proceedings of the Work-in-Progress Session of 32^th EuroMicro Conference, Cavtat, Croatia, ISBN 3-902457-11-2, pp. 53-54, Sept., 2006. (Doc File)

• P. Vouzis, L. G. Bleris, M. G. Arnold and M. V. Kothare, "A Custom-made Algorithm-Specific Processor for Model Predictive Control," in International Symposium of Industrial Electronics (ISIE'06), Montreal, Canada, 9-13 July, 2006. (PDF File)

• L. G. Bleris, P. D. Vouzis, M. G. Arnold and M. V. Kothare, "A Co-Processor FPGA Platform for the Implementation of Real-Time Model Predictive Control," in  American Control Conference 2006 (ACC'06), Minneapolis, Minnesota, 14-16 June, 2006. (PDF File)

• P. Vouzis and M. G. Arnold, "A Parallel Search Algorithm for CLNS Addition Optimization," in IEEE International Symposium on Circuits and Systems Kos, Greece, 21-24 May 2006. (PDF File)  (PowerPoint Presentation)

• L. G. Bleris, P. D. Vouzis, M. G. Arnold, M. V. Kothare, "Pathways for Optimization-Based Drug Delivery Systems and Devices," International Symposium on Advanced Control of Chemical Processes (ADCHEM'06), Gramado, Brazil, 2-5 April, 2006. (PDF File)

• P. Vouzis, L. G. Bleris, M. V. Kothare and M. G. Arnold, "Towards a Co-design Implementation of a System for Model Predictive Control," in AIChE annual meeting, Cincinnati, OH, November 2005. (AIChE Link) (PowerPoint Presentation)
  

• M. Arnold and J. Ruan, "Bipartite Implementation of the Residue Logarithmic Number System," SPIE Annual Meeting 2005, the International Symposium on Optical Science and Technology, pp. 196-205 San Diego, California, August 3, 2005. (Postscript File) (PowerPoint presentation)

• Mark G. Arnold and P. Leong. "Logarithmic Arithmetic for N-body Simulation," In Proceedings of the Work- in-Progress Session of 31^th EuroMicro Conference, pp. 24-25, Porto, Portugal, Sept. 3 2005.

• Mark G. Arnold, "Approximating Trigonometric Functions with the Laws of Sines and Cosines Using the Logarithmic Number System," In EuroMicro Symposium on Digital Systems Design, pp. 48-53, Porto, Portugal, Aug. 30 - Sept. 3 2005.

• Mark G. Arnold, "The Residue Logarithmic Number System: Theory and Implementation," In 17^th International Symposium on Computer Arithmetic, pp. 196-205, Cape Code, MA, 27-29 June 2005. (PDF File)

• P. Vouzis, Mark G. Arnold and V. Paliouras, "Using CLNS for FFTs in OFDM Demodulation of UWB Receivers," in IEEE International Symposium on Circuits and Systems Kobe, Japan, pp. 3954-3957, 23-26 May 2005. (PDF File)
  

• M. Arnold, "LPVIP: A Low-power ROM-less ALU for Low-Precision LNS," PATMOS 2004, 14th International Workshop on Power and Timing Modeling, Optimization and Simulation, Isle of Santorini, Greece, 15-17 September 2004. (Postscript File)

• J. Ruan and M. Arnold, "Threshold Mean Larger Ratio Motion Estimation in MPEG Encoding Using LNS,"  In the 14^th International Workshop on Power and Timing Modeling, Optimization and Simulation (PATMOS 2004), Isle of Santorini, Greece, 15-17 September 2004. (Postscript File)

• J. Garcia, M. G. Arnold, L. G. Bleris and M. V. Kothare, "LNS Architectures for Embedded Model Predictive Control Processors," in Proceedings of the 2004 International Conference on Compilers, Architecture, and Synthesis for Embedded Systems, pp. 79-84, Washington DC, USA, September 2004. (PDF File)
  

• M. Arnold, "Redundant logarithmic arithmetic for MPEG decoding," SPIE Annual Meeting 2004, the International Symposium on Optical Science and Technology, Denver, Colorado, 2-6 August 2004. (Postscript File)

• J. Ruan and M. Arnold, "New Cost Function for Motion Estimation in MPEG Encoding Using LNS," SPIE Annual Meeting 2004, the International Symposium on Optical Science and Technology, Denver, Colorado, 2-6 August 2004. (Postscript File)

• L. G. Bleris, M. V. Kothare, J. Garcia, and M. G. Arnold, "Embedded Model Predictive Control for System-On-a-Chip Applications," in 7th International Symposium on Dynamics and Control of Process Systems, Boston, MA, July 2004. (PDF File)
  

• M. Arnold, "Geometric-Mean Interpolation for Logarithmic Number Systems," IEEE 2004 International Conference on Circuits and Systems, Vancouver, Canada, 23-26 May 2004. (Postscript File)

• M. Arnold, "Asymmetric and Compressed Logarithmic Number Systems for a Multimedia Coprocessor," 37^th Asilomar Conference on Signals, Systems, and Computers, Pacific Grove CA, Nov. 9-12, 2003. (Invited Paper) (PDF File)

• J. Ruan and M. Arnold, "Combined LNS Adder/Subtractors for DCT Hardware," 1^st Workshop on Embedded Systems for Real-Time Multimedia, Newport Beach CA, pp. 118-123, Oct. 3-4, 2003. (PDF File) (PowerPoint presentation)

• J. Ruan and M. Arnold, "LNS Arithmetic for MPEG Encoding Using a Fast DCT," Proceedings of the Work-in-Progress Session of 29^th EuroMicro Conference, Belek (Antalya), Turkey, pp. 47-48, Sept. 6, 2003. (PDF File) (PowerPoint presentation)

• M. Arnold, "A VLIW Architecture for Logarithmic Arithmetic," 2003 EuroMicro Symposium on Digital Systems Design, Belek (Antalya), Turkey, pp. 294-301, Sept. 1-6, 2003. (30/85 long presentation) (PDF File)

• E. Walters, M. G. Arnold, M. J. Schulte, "Using Truncated Multipliers in DCT and IDCT Hardware Accelerators," Proceedings of SPIE: Advanced Signal Processing Algorithms, Architectures, and Implementations XIII, San Diego, CA, Aug. 2003. (PDF File)

• M. Arnold, "Iterative Methods for Logarithmic Subtraction," 2003 International Conference on Application Specific Architectures and Processors, The Hague, Netherlands, pp.315-325, June 24-26, 2003. (40/111) (PDF File)

• M. G. Arnold, J. Garcia and M. Schulte, "The Interval Logarithmic Number System," 16th IEEE International Symposium on Computer Arithmetic, Santiago de Compostela, Spain, pp. 253-261, June 15-18, 2003. (34/101) (PDF File)

• M. Arnold, "Avoiding Oddification to Simplify MPEG-1 Decoding with LNS," IEEE S, 2002 International Workshop on Multimedia Signal Processing, St. Thomas, Virgin Islands, Dec 9-11, 2002. (PDF File)

• M. Arnold, "Reduced Power Consumption for MPEG Decoding with LNS," Application Specific Architectures and Processors, San Jose, pp. 65-75, July 17-19, 2002. (36/66) (Postscript File) (PowerPoint presentation)

• M. Arnold, "LNS for Low Power MPEG Decoding," SPIE Advanced Signal Processing Algorithms Architecture and Implementations XII, Seattle, July 7-11, 2002. (Postscript File) (PowerPoint presentation)

• M. Arnold, "An Improved Cotransformation for Logarithmic Subtraction," International Symposium on Circuits and Systems, Scottsdale, AZ, vol. 2, pp. 752-755, May 2002. (Postscript File) (PowerPoint presentation)

• M. Arnold and M. Winkel, "A Single Multiplier Quadratic Interpolator for LNS Arithmetic," International Conference on Computer Design, Austin, pp. 178-183, Sept 23-26, 2001 (61/181). (Postscript File) (PowerPoint presentation)

• Mark G. Arnold, Thomas A. Bailey, John R. Cowles, Colin Walter, "Analysis of the Fast Fourier Transformation Implemented with the Complex Logarithmic Number System," SIPS 2001, Antwerp, Belgium, pp. 58-69, Sept 26-28, 2001. (24/80 long presentation) (Postscript File) (Word presentation)

• M. Arnold, "Design of a Faithful LNS Interpolator," EuroMicro Digital System Design, Warsaw, pp. 336-344, Sept 4-6, 2001. (21/79 long presentation) (Postscript File) (PowerPoint presentation)

• M. Arnold and M. Winkel, "Reconfiguring an FPGA-based RISC for LNS Arithmetic," Reconfigureable Technology: FPGAs and Reconfigurable Processors for Computing and Communications III, Proceedings of SPIE, Denver, vol. 4525, pp. 88-98, Aug 21-22, 2001. (Word Document) (PowerPoint presentation)

• N. Sample, M. Haines, M. Arnold, and T. Purcell, "Hybrid Search for Optimization of High-Dimensional k-d Trees," 5th WSES/IEEE World Multiconference on Circuits, Systems, Communications & Computers (CSCC 2001), Rethymnon, Crete, July 8-15, 2001 (withdrawn).

• M. Arnold, "Slide Rules for the 21st Century: Logarithmic Arithmetic as a High-speed, Low-cost, Low-power Alternative to Fixed Point Arithmetic," Second Online Symposium for Electronics Engineers, 2001, http://www.techonline.com/community/20140 (PowerPoint presentation)

• M. Arnold and C. Walter, "Unrestricted Faithful Rounding is Good Enough for Some LNS Applications," 15th Symposium on Computer Arithmetic, Vail, CO, pp. 237-245, June 11-13, 2001. (30/50) (Postscript File) (PowerPoint presentation)

• M. Arnold, "A Pipelined LNS ALU," Workshop on VLSI, Orlando, FL, pp. 155-161, April 19-20, 2001. (Word Document) (PowerPoint presentation)

• M. G. Arnold, C. Walter and F. Engineer, 2001, "Verilog Transcendental Functions for Numerical Testbenches," Proceedings of the Tenth International HDL conference, Santa Clara, California, March 1, 2001. (Word Document) (PowerPoint presentation)

• M. G. Arnold, J. J. Cupal and J. D. Shuler, "Blocking and Non-blocking Assignments in Explicit and Implicit Style Verilog," Proceedings of the Eight International HDL conference, Santa Clara, California, pp. 71-77, April 6-9, 1999. (PDF File)

• M. G. Arnold, N. J. Sample and J. D. Shuler, "Guidelines for Safe Simulation and Synthesis of Implicit Style Verilog," Proceedings of the Seventh International Verilog HDL Conference, Santa Clara, California, pp. 55-66, March 15-17, 1998. (PDF File)

• M. G. Arnold, T. A. Bailey, J. R. Cowles and M. D. Winkel, "Arithmetic Co-transformations in the Real and Complex Logarithmic Number Systems," 13th IEEE Symposium on Computer Arithmetic, Asilomar, California, pp. 190-199, July 6-9, 1997. (34/74)

• N. J. Sample and M. G. Arnold, "Javascript for Simulation Education," NAU Web 97 Conference, Flagstaff, Arizona, June 15-16, 1997.

• M. G. Arnold, T. A. Bailey, J. J. Cupal and M. D. Winkel, "On the Cost Effectiveness of Logarithmic Arithmetic for Back Propagation Training on SIMD Processors," 1997 International Conference on Neural Networks, Houston, Texas, June 9-12, 1997.

• M. G. Arnold and J. D. Shuler, "A Synthesis Preprocessor that Converts Implicit Style Verilog into One-hot Designs," Proceedings of the Sixth International Verilog HDL conference, Santa Clara, California, March 31-April 3, 1997. Best paper award. (PDF File)

• M. G. Arnold, A. Wallace, J. J. Cupal and J. R. Cowles, "Towards a Formal Model of Hardware Synthesized from Verilog," Proceedings of the 1996 International Verilog HDL Conference, February. 26-29 , Santa Clara, California, 1996.

• F. N. Engineer, M. G. Arnold, J. J. Cupal and M. Banki, "Implementing an Interface for a General Purpose Verilog/VHDL Emulator System," Proceedings of the 1995 PLD/FPGA Conference of Europe, London/Stockholm, May 10-16, 1995.

• M.G. Arnold, T.A. Bailey, J.R. Cowles, J.J. Cupal and F.N. Engineer, "Behavior to Structure: Using Verilog and In-circuit Emulation to Teach How an Algorithm Becomes Hardware," Proceedings of the 1995 International Verilog HDL Conference, Santa Clara, California, IEEE Computer Society Press, March 27-29, 1995. (PDF File)

• F. N. Engineer, J. J. Cupal and M. G. Arnold, "Simulation and In-Circuit Emulation of MSI Chips/ASIC Using a High Level Language in a Laboratory Environment," Proceedings of the 1995 International Conference on Simulation in Engineering Education, Las Vegas, The Society for Computer Simulation, January 15, 1995.

• M.G. Arnold, T.A. Bailey, J.R. Cowles, J.J. Cupal and A.W. Wallace, "A Purely Behavioral Data Structure for Accurate High Level Timing Simulation of Synchronous Design, Proceedings of the 1994 International Verilog HDL Conference, March 14-16, Santa Clara, California, IEEE Computer Society Press, pp. 101-107, 1994. (PDF File)

• M.G. Arnold, J.R. Cowles, R.D. Joslin and J.J. Cupal, "Simulation of Cooperating Algorithmic State Machines Using Verilog HDL," International Conference on Simulation and Hardware Description Languages (ICSHDL), January 24-26, Tempe, Arizona, (editors P.A. Widsey and D. Rhodes), The Society for Computer Simulation, pp. 63-69, 1994. (PDF File)

• M. Arnold, T. Bailey, J. Cowles and J. Cupal, "Implementing back propagation neural nets with logarithmic arithmetic," Proceedings Intern. AMSE Conference Neural Networks, San Diego, CA, May 29-31, (G. Mesnard and R. Swiniarski, Editors), vol. 1, pp. 75-86, 1991.

• M. Arnold, T. Bailey, J. Cowles and J. Cupal, "Redundant logarithmic number systems," IEEE Computer Society Press, Proceedings 9th Symposium on Computer Arithmetic, Santa Monica, CA, September 6-8, (M.D. Ercegovac and E. Swartzlander, Editors), pp. 144-157, 1989. (30/61)

• M. Arnold, T. Bailey and J. Cowles, 1988, "Improved Accuracy for Logarithmic Addition in DSP Applications," 1988 International Conference on Acoustics, Speech, and Signal Processing, IEEE, New York, NY, pp. 1714-1717, April 11-14, 1988.

• M. G. Arnold, 1994, U. S. Patent 5,337,266, Method and Apparatus for Fast Logarithmic Addition and Subtraction.

• M. G. Arnold, 1986, U. S. Patent 4,623,881, Method and Apparatus for Increasing the Number of Characters per line in a Digitally Generated Display on a Limited Bandwidth Raster Scanned Device.

• M. G. Arnold and M. D. Winkel, 1985, U. S. Patent 4,558,176, Computer Systems to Inhibit Unauthorized Copying, Unauthorized Usage, and Automated Cracking of Protected Software.

• M. L. Cook and M. G. Arnold, 1981, "A Structured APL Preprocessor," SIGPLAN Notices 16, Association for Computing Machinery, 22-31.

• M. G. Arnold, 1976, "What is APL?," BYTE 1, No. 15, BYTE Publications (Peterborough, NH), pp. 20-24, 123-126, November 1976.

• N. Wadsworth and M. G. Arnold, SCELBAL, BYTE, BYTE Publications (Peterborough, NH), no 10, pp. 82-86, June 1976.

• M. Braunstein, C. Mealey and M. Arnold, LawLine User's Manual, Law Line (Columbus, OH) , 1987.

• M. G. Arnold, ILLRKS User's Manual, Arnold Library Systems (Laramie, WY) , 1986.

• M. G. Arnold and N. Greene, EasyGen User's Manual, Arnold Library Systems (Laramie, WY) , 1985.

• M. G. Arnold and N. Wadsworth, SCELBAL: A Higher Level Language for 8008/8080 Systems, Scelbi Computer Consulting (Milford, CT) , 1976.

• J. Cowles and M. Arnold, Towards reusable libraries for Acl2: Progress Report 2, Internal Note 277, Computational Logic, Inc., Austin, TX, 1993.

• J. Cowles and M. Arnold, Towards reusable libraries for Acl2: Progress Report 1, Internal Note 273, Computational Logic, Inc., Austin, TX, 1993.

• M. G. Arnold and S. B. Taylor, Introduction to Computer Organization Using the PDP8. (Used to teach COSC 2150 since 1994).

• M. G. Arnold, Computer Science 301-401 Laboratory Manual (Used to teach introductory COSC sections 1983-1986).

Section 2: Prof. Michael J. Schulte

Some of the older papers do not have electronic versions available for downloading. If you would like a copy of one of these papers, please send email to mschulte@eecs.lehigh.edu.

• M. J. Schulte, P. I. Balzola, A. Akkas, and R. W. Brocato, ``Integer Multiplication with Overflow Detection or Saturation,'' IEEE Transactions on Computers, vol. 49, July 2000. (Postscript File)

• M. J. Schulte and E. E. Swartzlander, Jr., ``A Family of Variable-Precision, Interval Arithmetic Processors,'' IEEE Transactions on Computers, vol. 49 May 2000. (PDF File)

• M. J. Schulte and James E. Stine, ``Approximating Elementary Functions with Symmetric Bipartite Tables,'' in IEEE Transactions on Computers, no. 8, vol. 48, pp. 842-847, August, 1999. (PDF File)

• J. E. Stine and M. J. Schulte, ``The Symmetric Table Addition Method for Accurate Function Approximation,'' in Journal of VLSI Signal Processing, vol. 21, no. 2, pp. 167-177, June, 1999. (Postscript File)

• M. J. Schulte, A. Akkas, V. Zelov, and J. C. Burley, ``The Interval-Enhanced GNU Fortran Compiler,'' Reliable Computing, Vol. 5., No. 3, pp. 311-322, 1999. Also published in Developments in Reliable Computing (T. Csendes ed.) pp. 311-322, Kluwer Academic Publishers, 1999. (Postscript File)

• M. J. Schulte, K. C. Bickerstaff, and E. E. Swartzlander, Jr., `` Hardware Interval Multipliers,'' Journal of Theoretical and Applied Informatics, Vol. 3, No. 2, pp. 73-90, 1997. (Postscript File)

• T. Lynch and M. J. Schulte, ``Software for High Radix On-line Arithmetic,'' Reliable Computing, Vol. 2, No. 2, pp. 133-138, 1996.

• M. J. Schulte and E. E. Swartzlander, Jr., ``Variable-Precision, Interval Arithmetic Coprocessors,'' Reliable Computing, Vol 2., No. 1, pp. 47-62, 1996.

• T. Lynch and M. J. Schulte, ``A High Radix On-line Arithmetic for Credible and Accurate Computing,'' Journal of Universal Computer Science, Vol. 1, No. 7, pp. 435-449, 1995.

• K. C. Bickerstaff, M. J. Schulte, and E. E. Swartzlander, Jr., ``Parallel Reduced Area Multipliers,'' Journal of VLSI Signal Processing, Vol. 9, No. 3, pp. 181-192, April, 1995.

• M. J. Schulte and E. E. Swartzlander, Jr., ``A Software Interface and Hardware Design for Variable-Precision Interval Arithmetic,'' Reliable Computing, Vol. 1, No. 3, pp. 324-342, 1995 (Best Student Paper Award).

• M. J. Schulte and E. E. Swartzlander, Jr., ``Hardware Designs for Exactly Rounded Elementary Functions,'' IEEE Transactions on Computer, Special Issue on Computer Arithmetic, Vol. 43, No. 8, pp. 964-973, 1994.

• M. J. Schulte, J. Omar, and E. E. Swartzlander, Jr., ``Optimal Initial Approximations for the Newton-Raphson Division Algorithm,'' Computing, Vol. 53, No. 3, pp. 233-242, 1994.

• M. J. Schulte and E. E. Swartzlander, Jr., ``Parallel Hardware Designs for Correctly Rounded Elementary Functions,'' Interval Computations, Vol. 4, No. 4, pp. 65-88, 1993.

• M. J. Schulte, V. Zelov, G. W. Walster and D. Chiriaev, ``Single-Number Interval I/O,'' Developments in Reliable Computing (T. Csendes ed.) pp. 141-148, Kluwer Academic Publishers, 1999. (Postscript File)

• M. J. Schulte, ``Variable-Precision, Interval Arithmetic Processors,'' Application Specific Processing, Kluwer Academic Publishers, Boston, pp. 1-28, 1997. (Postscript File)

• M. J. Schulte and E. E. Swartzlander, Jr., ``Software and Hardware Techniques for Accurate, Self-Validating Arithmetic,'' Applications of Interval Computations, Kluwer Academic Publishers, Boston, pp. 381-404, 1996. (Postscript File)

• M. J. Schulte and E. E. Swartzlander, Jr., ``A Processor for Accurate, Self-Validating Computing,'' Scientific Computing and Validated Numerics, Akademie Verlag, pp. 25-31, 1996.

• M. J. Schulte and E. E. Swartzlander, Jr., ``A Coprocessor for Accurate and Reliable Computing,'' Numerical Methods and Error Bounds, Akademie Verlag, pp. 217-223, 1996.

• M. A. Erle, M. J. Schulte, B. J. Hickman, ``Decimal Floating-Point Multiplication Via Carry-Save Addition,"  accepted for publication in the Proceedings of the 18^th IEEE Symposium on Computer Arithmetic, Montpellier, France,  25-27 June 2007. (PDF File)

• M. A. Erle, E. M. Schwarz, M. J. Schulte, ``Decimal Multiplication With Efficient Partial Product Generation," Proceedings of the 17^th IEEE Symposium on Computer Arithmetic, pp. 21-28, Cape Cod, MA, 27-29 June 2005. (PDF File)

• R. D. Kenney, M. J. Schulte, M. A. Erle, ``A High-Frequency Decimal Multiplier," Proceedings of the IEEE International Conference on Computer Design, pp. 26-29,  San Jose, California, 11-13 Oct. 2004. (PDF File)

•  M. A. Erle, M. J. Schulte, ``Decimal Multiplication Via Carry-Save Addition," Proceedings of the IEEE International Conference on Application-Specific Systems, Architectures, and Processors, pp. 348-358,  The Hague, The Netherlands, 24-26 June 2003. (PDF File)

• M. A. Erle, M. J. Schulte, J. M Linebarger, ``Potential Speedup Using Decimal Floating-Point Hardware,'' Conference Record of the Thirty-Sixth Asilomar Conference on Signals, Systems and Computers, Vol. 2, pp.1073-1077, Pacific Grove, California, 3-6 Nov. 2002. (PDF File)

• J. E. Garcia and M. J. Schulte, ``A Combined 16-Bit Binary and Dual Galois Field Multiplier,'' Proceedings of the IEEE Workshop on Signal Processing Systems, San Diego, California, October, 2002. (Postscript File)

• E. G. Walters, J. Glossner, M. J. Schulte, ``Automatic VHDL Model Generation of Parameterized FIR Filters,'' Proceedings of Embedded Processor Design Challenges: Systems, Architectures, Modeling, and Simulation - SAMOS, July, 2002. (PDF File)

• E. G. Walters and M. J. Schulte, ``Design Tradeoffs Using Truncated Multipliers in FIR Filter Implementations,'' Proceedings of SPIE : Advanced Signal Processing Algorithms, Architectures, and Implementations, Seattle, Washington, July, 2002. (PDF File)

• M. R. Pillmeier and M. J. Schulte, ``Design Alternatives for Barrel Shifters and Rotators,'' Proceedings of SPIE : Advanced Signal Processing Algorithms, Architectures, and Implementations, Seattle, Washington, July, 2002. (PDF File)

• J. Glossner, M. Schulte, and S. Vassailiadis, ``A Java-enabled DSP'', Embedded Processor Design Challenges: Systems, Architectures, Modeling, and Simulation - SAMOS}, Lecture Notes in Computer Science, Springer, vol. 2268, pp. 307-326, 2002. (PDF File)

• E. G. Walters, J. Schlessman, and M. J. Schulte, ``Combined Unsigned and Two's Complement Hybrid Squarers,'' in Proceedings of the Thirty Fifth Asilomar Conference on Signals, Systems, and Computers, Pacific Grove, California, IEEE Press, pp. 861-866, November, 2001. (Postscript File)

• M. Gok, M. J. Schulte, and P. I. Balzola, ``Efficient Integer Multiplication Overflow Detection Circuits,'' in Proceedings of the Thirty Fifth Asilomar Conference on Signals, Systems, and Computers, Pacific Grove, California, IEEE Press, pp. 1661-1665, November, 2001. (Postscript File)

• P. I. Balzola, M. J. Schulte, J. Ruan, and J. Glossner, and E. Hokenek, ``Design Alternatives for Parallel Saturating Multioperand Adders,'' Proceedings of the International Conference on Computer Design, Austin, TX, IEEE Computer Society Press, pp. 172-177, September, 2001. (PDF File)

• K. E. Wires, M. J. Schulte, and J. E. Stine, ``Combined IEEE Compliant and Truncated Floating Point Multipliers for Reduced Power Dissipation,'' in Proceedings of the International Conference on Computer Design, Austin, TX, IEEE Computer Society Press, pp. 497-500, September, 2001. (Postscript File)

• K. E. Wires, M. J. Schulte, and D. McCarley, ``FPGA Resource Reduction Through Truncated Multiplication" Proceedings of the 11th International Conference on Field Programmable Logic and Applications, Belfast, Ireland, pp. 574-583, August, 2001. (PDF File)

• N. Koc-Sahan, J. Schlessman, and M. J. Schulte, ``Symmetric Table Addition Methods for Neural Network Approximations,'' Proceedings of SPIE : Advanced Signal Processing Algorithms, Architectures, and Implementations XI, San Diego, CA, pp. 126-133, July, 2001. (Postscript File)

• K. C. Bickerstaff, E. E. Swartzlander, Jr., and M. J. Schulte,` ``Analysis of Column Compression Multipliers,'' Proceedings of the 15th IEEE Symposium on Computer Arithmetic, Vail, Colorado, IEEE Computer Society Press, pp. 33-39, June 2001. (PDF File)

• J. Glossner, D. Routenberg, E. Hokenek, M. Moudgill, M. Schulte, P. I. Balzola, and S. Vassailiadis, ``Towards Very High Bandwidth Wireless Battery Powered Devices,'' IEEE Computer Society Workshop on VLSI, Orlando, Florida, IEEE Computer Society Press, pp. 3-9, April, 2001.

• K. E. Wires, M. J. Schulte and J. E. Stine, ``Variable-Correction Truncated Floating Point Multipliers,'' Proceedings of the Thirty Fourth Asilomar Conference on Signals, Systems, and Computers, Pacific Grove, California, pp. 1344-1348, IEEE Press, November, 2000.

• M. J. Schulte, P. I. Balzola, J. Ruan, and J. Glossner, ``Parallel Saturating Multioperand Adders,'' Proceedings of the International Conference on Compilers, Architectures and Synthesis for Embedded Systems, ACM Press, San Jose, California, pp. 172-179, November, 2000.

• M. J. Schulte, M. Gok, P. I Balzola, and R. W. Brocato, ``Combined Unsigned and Two's Complement Saturating Multipliers,'' accepted for publication in Proceedings of SPIE : Advanced Signal Processing Algorithms, Architectures, and Implementations, San Diego, CA, July, 2000 (Postscript File) San Diego, CA, pp. 185-196, July, 2000.

• J. Hormigo, J. Villalba, and M. Schulte, ``A Hardware Algorithm for Variable-Precision Logarithm,'' accepted for publication in Proceedings of the IEEE International Conference on Application-Specific Systems, Architectures, and Processors, Boston, July, 2000. (Postscript File)

• A. Goldovsky, B. Patel, M. Schulte, R. Kolagotla, H. Srinivas, and G. Burns, ``Design and Implementation of a 16 by 16 Low Power Two's Complement Multiplier,'' Proceedings of the 2000 IEEE International Symposium on Circuits and Systems, Geneva, Switzerland May, 2000. (Gzipped Postscript File)

• J. Hormigo, J. Villalba, and M. Schulte, ``A Hardware Algorithm for Variable-Precision Division,'' Proceedings of the 4th Conference on Real Numbers and Computers, Dagstuhl, Saar, Germany April, 2000. (Postscript File)

• D. Batten, S. Jinturkar, J. Glossner, M. Schulte, and P. D'Arcy, ``A New Approach to DSP Intrinsic Functions,'' accepted for publication in Proceedings of the IEEE Thirty-Third Hawaii International Conference on System Sciences, Hawaii, January, 2000. (Postscript File)

• D. Batten, S. Jinturkar, J. Glossner, M. Schulte, R. Peri and P. D'Arcy, ``Interactions Between Optimizations and a New Type of DSP Intrinsic Function'', in Proceedings of the International Conference on Signal Processing Applications and Technologies, Orlando, Florida, November, 1999 (in press). Shortened version published as D. Batten and P. D'arcy, ``Intrinsic Functions Boost Compilers'', in Electrical Engineering Times, p. 104, vol. 1085, November, 1, 1999. (Postscript File)

• K. E. Wires, M. J. Schulte, and L. P. Marquette, ``Combined Unsigned and Two's Complement Squarers,'' Proceedings of the Thirty Third Asilomar Conference on Signals, Systems, and Computers, Pacific Grove, California, pp. 1215-1219, October, 1999. (Postscript File)

• M. J. Schulte, ``Computer Architecture Web Page Design Projects,'' in Proceedings of the 1999 Frontiers in Education Conference, San Juan, Puerto Rico, pp. 12a4-18 - 12a6-21, November, 1999 (PDF File)

• M. J. Schulte, C. Power, C. Andrews, T. Hamilton, W. Muniz, H. Haileselassie, W. Haileselassie, K. Mlodossich, C. Leveque, E. Smith, and A. Bristol, ``National Society of Black Engineers Community Outreach Program,'' in Proceedings of the 1999 Frontiers in Education Conference, San Juan, Puerto Rico, pp. 12d4-1 - 12d4-6, November, 1999. (PDF File)

• M. J. Schulte and K. E. Wires, ``Efficient Second Order Approximations for Reciprocals and Square Roots,'' in {\em Proceedings of SPIE : Advanced Signal Processing Algorithms, Architectures, and Implementations}, vol. 3807, pp. 10--18, Denver, July, 1999. (Postscript File)

• M. J. Schulte, A. Akkas, V. Zelov, and J. C. Burley, ``Compiler Support for Interval Arithmetic,'' Proceedings of the 16th IEEE Instrumentation and Measurement Technology Conference, Venice, Italy, pp. 1189-1193, May, 1999. (Postscript File)

• M. J. Schulte and K. E. Wires, ``High-Speed Inverse Square Roots,'' Proceedings of the 14th IEEE Symposium on Computer Arithmetic, Adelaide, Australia, pp. 124-131, April, 1999. (Postscript File)

• N. Yadav, J. Glossner, and M. J. Schulte, ``Parallel Saturating Fractional Arithmetic Units,'' Proceedings of the Ninth Great Lakes Symposium on VLSI, Ann Arbor, Michigan, pp. 214-217, March, 1999. (Postscript File)

• M. J. Schulte, J. G. Jansen, and J. E. Stine, ``Reduced Power Dissipation Through Truncated Multiplication,'' Proceedings of the IEEE Alessandro Volta Memorial International Workshop on Low Power Design, Como, Italy, March, pp. 61-69, 1999. (Postscript File)

• J. E. Stine and M. J. Schulte, ``A Combined Interval and Floating Point Divider,'' Proceedings of the Thirty Second Asilomar Conference on Signals, Systems, and Computers, Pacific Grove, California, vol. 1, pp. 218-222, November, 1998. (Postscript File)

• J. E. Stine and M. J. Schulte, ``A Combined Interval and Floating Point Multiplier,'' Proceedings of 8th Great Lakes Symposium on VLSI, Lafayette, LA, pp. 208-213, February, 1998. (Postscript File)

• M. J. Schulte, J. E. Stine, and K. E. Wires, ``High-Speed Reciprocal Approximations ,'' Proceedings of the Thirty First Asilomar Conference on Signals, Systems, and Computers, Pacific Grove, California, vol. 2, pp. 1183-1187, November, 1997. (Postscript File)

• M. J. Schulte and James E. Stine, ``Accurate Function Approximations by Symmetric Table Lookup and Addition,'' Proceedings of the 11th International Conference on Application-Specific Systems, Architectures, and Processors, Zurich, Switzerland, pp. 144-153, July, 1997. (Postscript File)

• M. J. Schulte and James E. Stine, ``Symmetric Bipartite Tables for Accurate Function Approximation,'' Proceedings of the 13th IEEE Symposium on Computer Arithmetic, Pacific Grove, California, pp. 175-183, July, 1997. (Postscript File)

• M. J. Schulte, K. C. Bickerstaff, and E. E. Swartzlander, Jr., ``Hardware Designs for Interval Multiplication,'' Proceedings of the II Workshop on Computer Arithmetic, Interval and Symbolic Computation, Recife, Brazil, pp. 85-87, August, 1996.

• M. J. Schulte and E. E. Swartzlander, Jr., ``A Coprocessor Design for Accurate and Reliable Computing,'' Proceedings of the International Conference on Computer Design, Austin, TX, pp. 686-691, October, 1995.

• T. Lynch, A. Ahmed, M. Schulte, T. Callaway, and R. Tisdale, ``The K5 Transcendental Functions,'' Proceedings of the 12th IEEE Symposium on Computer Arithmetic, Bath, England, pp. 163-171, July, 1995.

• M. J. Schulte and E. E. Swartzlander, Jr., ``Hardware Designs and Arithmetic Algorithms for a Variable-Precision, Interval Arithmetic Coprocessor,'' Proceedings of the 12th IEEE Symposium on Computer Arithmetic, Bath, England, pp. 222-229, July, 1995.

• M. J. Schulte and E. E. Swartzlander, Jr., ``A Staggered Interval Arithmetic Processor,'' Proceedings of the 1995 International Conference on Application Specific Array Processors, Strasbourg, France, pp. 104-112, July, 1995.

• M. J. Schulte and E. E. Swartzlander, Jr., ``Designs and Applications for Variable-Precision, Interval Arithmetic Coprocessors,'' Reliable Computing, International Workshop on Applications of Interval Computations, El Paso, Texas, pp. 166-172, February, 1995.

• M. J. Schulte and E. E. Swartzlander, Jr., ``A Variable-Precision, Interval Arithmetic Processor,'' Proceedings of the 1994 International Conference on Application Specific Array Processors, San Francisco, pp. 248-258, September, 1994.

• K. C. Bickerstaff, M. J. Schulte, and E. E. Swartzlander, Jr., ``Reduced Area Multipliers,'' Proceedings of the 1993 International Conference on Application Specific Array Processors, Venice, Italy, pp. 478-489, October, 1993.

• M. J. Schulte and E. E. Swartzlander, Jr., ``Truncated Multiplication with Correction Constant,'' VLSI Signal Processing VI, IEEE Workshop on VLSI Signal Processing, Eindhoven, Netherlands, pp. 388-396, October, 1993.

• M. J. Schulte and E. E. Swartzlander, Jr., ``Exact Rounding of Certain Elementary Functions,'' Proceedings of the 11th IEEE Symposium on Computer Arithmetic, Windsor, Ontario, Canada, pp. 138-145, July, 1993.

• M. J. Schulte, K. E. Wires and J. E. Stine, ``Variable-Correction Truncated Floating Point Multipliers,'' submitted to The Thirty Fourth Asilomar Conference on Signals, Systems, and Computers, Pacific Grove, California, October, 2000. (Postscript File)

• A. Akkas, J. E. Stine, and M. J. Schulte, ``Evaluating the Impact of Accurate Branch Prediction on Interval Software,'' accepted for publication in The International Symposium on Scientific Computing, Computer Arithmetic, and Validated Numerics, Karlsruhe, Germany, September, 2000. (Postscript File)

• J. E. Stine, A. Akkas, and M. J. Schulte, ``A Case for Interval Hardware on Superscalar Processors,'' accepted for publication in The International Symposium on Scientific Computing, Computer Arithmetic, and Validated Numerics, Karlsruhe, Germany, September, 2000. (Postscript File)

• J. Hormigo, J. Villalba, and M. Schulte, ``Variable-Precision Exponential Evaluation,'' accepted for publication in The International Symposium on Scientific Computing, Computer Arithmetic, and Validated Numerics, Karlsruhe, Germany, September, 2000. (Postscript File)

• J. Garcia, Applying the Logarithmic Number System to Application-Specific Designs, Doctoral Dissertation, Lehigh University, 2004. (PDF File)
• M. J. Schulte, A Variable-Precision, Interval Arithmetic Processor, Doctoral Dissertation, University of Texas at Austin, 1996. (Postscript File)
• K. E. Wires, Arithmetic Units for Digital Signal Processing and Multimedia , Doctoral Dissertation, Lehigh University, 2001. (Postscript File)

• M. Gok, Integer Multiplication with Overflow Detection or Saturation, Masters Thesis, Lehigh University, 2000. (Postscript File)

• N. Yadav, Architectural Design Options for ATM Switches, Masters Thesis, Lehigh University, 1999. (PDF File)

• A. Goldovsky, A 1.0 Nanosecond 32-Bit Prefix Tree Adder in 0.25 Micron Static CMOS, Masters Thesis, Lehigh University, 1999.

• G. Williams, Processor Support for Interval Arithmetic, Masters Thesis, Lehigh University, 1998. (PDF File)

• L. Fenstermaker, Current Mode Sense Amplifiers Applied to Dual Port Register Files, Masters Thesis, Lehigh University, 1998. (Gzipped Postscript File)