Using RLNSTOOL
RLNSTOOL generates several Verilog files that correspond to the information specified in rlnstool.h .
A first set of files contains synthesizable Verilog modules for basic RLNS operations using binary-encoded moduli:
- add2rlns.v defines add_residueLNS(s2,a2,b2);
- Add inputs a2 and b2 producing the output s2 using the improved algorithm described in the paper .
- nad2rlns.v defines an alternative for add_1hot_residueLNS(s2,a2,b2);
- Add inputs a2 and b2 producing the output s2 using a naive algorithm.
- alt2rlns.v defines yet another alternative for add_1hot_residueLNS(s2,a2,b2);
- Add inputs a2 and b2 producing the output s2 using an alternative Verilog coding for the naive algorithm.
- mul2rlns.v defines mul_residueLNS(p2,a2,b2);
- Multiply inputs a2 and b2 producing the output p2.
- div2rlns.v defines div_residueLNS(q2,a2,b2);
- Divide inputs a2 and b2 producing the output q2.
The bitwidth of the binary-encoded RLNS variables ( a2, b2, ... ) will be 1 (for the value sign) plus the sum of the bit widths of each of the moduli.
For example, the moduli 4, 3, 5 and 7 used in the paper require 11 bits. Each file will have a macro defined to avoid mixing incompatible files.
For the example moduli, this macro must be `MODULI_4_3_5_7 in every binary-encoded-moduli file.
Another similar set of files that contain synthesizable Verilog modules for one-hot-encoded moduli:
- add1rlns.v defines add_1hot_residueLNS(s1,a1,b1);
- Add inputs a1 and b1 producing the output s1 using the improved algorithm described in the paper .
- nad1rlns.v defines an alternative for add_1hot_residueLNS(s2,a2,b2);
- Add inputs a1 and b1 producing the output s1 using a naive algorithm.
- alt1rlns.v defines yet another alternative for add_1hot_residueLNS(s2,a2,b2);
- Add inputs a1 and b1 producing the output s1 using an alternative Verilog coding for the naive algorithm.
- mul1rlns.v defines mul_1hot_residueLNS(p1,a1,b1);
- Multiply inputs a1 and b1 producing the output p1.
- div1rlns.v defines div_1hot_residueLNS(q1,a1,b1);
- Divide inputs a1 and b1 producing the output q1.
The bitwidth of the one-hot-encoded RLNS variables ( a1, b1, ... ) will be 1 (for the value sign) plus the sum of each of the moduli.
For example, the moduli 4, 3, 5 and 7 used in the paper require 20 bits. Each file will have a macro defined
to avoid mixing incompatible files.
For the example moduli, this macro must be `MODULI_ONEHOT_4_3_5_7 in every one-hot-encoded-moduli file.
Because of the underlying limitations of residue integers, RLNS cannot detect underflow and overflow on the fly, the way conventional LNS and floating point can.
To assist in finding bugs that result from this, an optional macro may be defined that allows simulation-time
testing of the result of the above modules. (This macro should not be defined during synthesis). This macro is
`CHECK_RELERR, which should be defined to be a real number greater than the relative error inherent in the choice of the moduli, BASE and ZSCALE.
When errors greater than this occur (probably due to overflow or underflow), an error messsage is printed, allowing the designer to
identify the cause, and correct the problem either by making appropriate changes to the algorithm to avoid the overflow,
or by increasing the dynamic range of the RLNS (using larger moduli or a bigger BASE or a smaller ZSCALE).
Since the RLNS variables have three levels of abstraction (logarithm, residue and moduli), some routines are generated by RLNSTOOL for simulation-time
printing and conversion of RLNS values:
- cvt1rlns.v defines the function cvt_1hot_residueLNS(a1);
- Convert one-hot-encoded-moduli a1 into a Verilog real.
- pri1rlns.v defines the function print_1hot_residueLNS(a1);
- Print one-hot-encoded-moduli a1 as its value sign and RNS logarithm as well as the associated real.
- cvt2rlns.v defines the function cvt_residueLNS(a1);
- Convert binary-encoded-moduli a2 into a Verilog real.
- pri2rlns.v defines the function print_residueLNS(a1);
- Print binary-encoded-moduli a2 as its value sign and RNS logarithm as well as the associated real.